Projects
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Q-Cache - A Deep Q-learning guided Cache replacement policy Github
Designed a Deep Reinforcement Learning–based cache replacement policy that learns how to evict cache blocks and compare its performance with traditional methods such as LRU, LFU, and Random and evaluated Q-Cache across multiple synthetic access patterns such as Zipf, Loop, Bursty, Markov, Stride, and Mixed traces.
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Research Implementation - CycleGANs Github
Re-implemented CycleGAN from the original paper (Zhu et al.) for unpaired image-to-image translation (Horses to Zebras and vice versa) and achieved realistic style transfer with preserved structure in training outputs after 45 epochs.
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Matrix Multiplication on FPGA Github
Implemented a matrix multiplication algorithm in Verilog HDL and a C kernel for FPGA-based hardware acceleration using Vitis IDE. Deployed the design on the Kria KV260 Vision AI Starter Kit and verified functionality and performance.
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Chisel Digital Designs Github
Learned Chisel HDL and its functions. Designed and verified basic digital circuits, including adders and encoders, using ScalaTest simulations.
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E-yantra - Astro-Tinker Robot Github
Constructed a Pick and Place and Line Following robot to use in an arena that represents an scenario of a space station with a team of four and implemented a single cycle RISC-V RV32I core, written in Verilog HDL that can execute C codes, compiled into hexadecimal instructions for the CPU using the RISC-V cross-compiler. We executed a Dijkstra's Algorithm written in C on the RISC-V CPU to find the shortest path between two locations in the arena and navigation was achieved by a Line following Algorithm, implementing a PID controller for the same.This was programmed on the DE0-Nano development board consisting of Intel Cyclone-IV FPGA with the help of Intel Quartus Prime Lite and Modelsim Altera
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RISC-V CPU Github
Designed a RISC-V core supporting RV32IM extensions in Verilog HDL from scratch. This CPU was tested on UPduino 3.0 board using Yosys suite and IceStorm toolchain by successfully executing a fibonacci series by connecting output GPIOs to a Seven Segment Display.